1. Field of the Invention
The present invention relates to a multilevel interconnecting structure in a semiconductor device and a method of forming the same and, more particularly, to a multilevel interconnecting structure in a semiconductor device, in which the dielectric constant of an insulating interlayer is decreased at the same time the insulating interlayer is planarized, and a method of forming the same.
2. Description of the Prior Art
Recently, as semiconductor integrated circuits continue to be miniaturized and increase in degree of integration, the miniaturization of interconnection pitches and the formation of multilevel interconnections have significantly progressed. Under the circumstances, in logic semiconductor devices the dielectric constant of an insulating interlayer is required to be decreased because it is essential to reduce the propagation delay of signals. Therefore, it is being studied to form a fluorine-doped silicon oxide film (to be referred to as an SiOF film hereinafter) as a low dielectric film by supplying a fluorine-containing gas by using a high-density plasma CVD (to be referred to as HDP-CVD) apparatus. This HDP-CVD SiOF film as a low dielectric film can be well buried in an inter-interconnection space of 0.25 .mu.m or less which is difficult to fill with a silicon oxide film formed by plasma excitation CVD (to be referred to as PE-CVD hereinafter) using a conventional reaction gas such as TEOS (tetraethylorthosilicate). This is so because when a film is deposited by HDP-CVD, a bias is applied to a substrate to perform sputter etching simultaneously with the film formation. In this method, particularly the edges of the silicon oxide film deposited on an interconnection are selectively etched to improve the burying property of the film.
In memory semiconductor devices, particularly dynamic random access memories (DRAMS), as in logic semiconductor devices, the miniaturization of interconnections and the formation of multilevel interconnections have advanced, and especially the burying property of an insulating interlayer is a problem. However, an apparatus such as an HDP-CVD apparatus which generates high-density plasma has a large sputter etching effect as described above. This extremely lowers the deposition rate of a film and tends to increase the fabrication cost. Accordingly, a method is being studied which improves the burying property of an insulating interlayer by supplying a fluorine-based gas into a parallel plate PE-CVD apparatus to form an SiOF film.
Normally, in logic semiconductor devices an SiOF film can be easily planarized by chemical mechanical polishing (CMP). However, in DRAMs among other memory semiconductor devices, a capacitor is often formed on a MOS transistor in a memory cell. To obtain a large area of a capacitor electrode in a narrow region, the capacitor electrode tends to vertically extend. This increases the step between the memory cell and its peripheral circuit. When an insulating interlayer on the interconnection is polished by CMP, this step is difficult to reduce. This will be described with reference to FIGS. 1A and 1B. FIGS. 1A and 1B are schematic sectional views showing a part of a DRAM.
As shown in FIG. 1A, a first undercoating insulating film 101 is formed on a semiconductor substrate 100. In a memory cell, a second undercoating insulating film 102 is so formed as to cover a capacitor. An interconnecting layer 103 is formed on the surface of the first undercoating insulating film 101 in a peripheral circuit of the DRAM. Also, an interconnecting layer 103a is formed on the second insulating film 102 in the memory cell of the DRAM.
An insulating interlayer 104 is so deposited as to cover the interconnecting layers 103 and 103a formed in the memory cell and the peripheral circuit having a step between them as described above. This insulating interlayer 104 is an SiOF film.
Next, as shown in FIG. 1B, the insulating interlayer 104 is polished by CMP. However, a step is present between the interconnecting layer 103 in the peripheral circuit and the interconnecting layer 103a in the memory cell. Therefore, even when the insulating interlayer 104 on the interconnecting layer 103a in the memory cell is polished and planarized, the insulating interlayer 104 in the peripheral circuit is not polished. Consequently, the insulating interlayer 104 in the peripheral circuit becomes uneven in accordance with the pattern of the interconnecting layer. This unevenness increases as the semiconductor device structure continues to shrink in feature size as described above.
In addition to the method of forming an insulating interlayer as described above, it is possible to use a method in which a planarizing film is stacked on an insulating interlayer and etched back to planarize the surface of the insulating interlayer. As the planarizing film, a photoresist or SOG (Spin On Glass) is used. A method using a photoresist as the planarizing film is described in detail in Japanese Unexamined Patent Publication No. 5-226480. Therefore, a method of etching back an SOG planarizing film will be described below with reference to FIGS. 2A to 2D. FIGS. 2A to 2D are sectional views showing steps of forming this insulating interlayer in order.
As shown in FIG. 2A, an undercoating insulating film 202 is formed by, e.g., a silicon oxide film on a silicon substrate 201. Subsequently, a first interconnecting layer 203 is formed on the undercoating insulating film 202, and an antireflection film 204 is formed on top of the first interconnecting layer 203. A first protective insulating film 205 is then deposited so as to cover the entire surface.
Next, an SiOF film 206 is deposited on the protective insulating film 205. An SOG film 207 is formed on this SiOF film 206 to planarize the surface of the SiOF film 206.
As shown in FIG. 2B, the SOG film 207 and the surface of the SiOF film 206 are etched back. This etching back is done by a method of dry etching using a fluorine-based gas. Next, ad shown in FIG. 2C, a second protective insulating film 208 is deposited on the etched back SiOF film 206. This second protective film 208 is also a silicon oxide film formed by PE-CVD.
As shown in FIG. 2D, through holes 209 are formed in predetermined regions of the second protective insulating film 208 and the SiOF film 206. Finally, a second interconnecting layer 210 electrically connecting with the first interconnecting layer 203 is formed.
In the above prior art, when the etching of the SOG film proceeds to expose the SiOF film and the SOG film in the etching back step, the SOG film is rapidly etched by fluorine released from the surface of the SiOF film.
This makes it difficult to planarize the step of the SiOF film in the step of forming the SOG film on the SiOF film and etching back the films by dry etching. Consequently, the overlying interconnecting layer formed on the SiOF film is broken or short-circuited. Alternatively, good image forming performance becomes difficult to obtain in photolithography in the pattern formation in the next step.
Also, after the formation of the SiOF film, atmospheric water or water in the SOG film readily enters and remains in the SiOF film. This increases the amount of water contained in the SiOF film. This water oozes out from the side walls of the through holes when the through holes are filled with a metal film. Consequently, the resistance of the interconnection in the through hole increases, or the interconnection breaks. Furthermore, this increase of the water amount in the SiOF film increases the relative dielectric constant of the film to make the dielectric constant between the interconnecting layers difficult to decrease.